This invention relates generally to a tool for estimating the power dissipation in a proposed electronic system design such as a microprocessor.
Designers of complex electronic systems such as microprocessors are faced with a myriad of tradeoffs. Good system design usually involves making the best trade off for the particular circumstances involved. For example, a prime design criteria in microprocessor design is processor speed or performance. This criteria needs to be balanced with considerations relating to die or chip size. Similarly, many systems are designed to enhance the ultimate testability of the design and therefore the ultimate reliability of the parts.
A number of design tools are available to enable the early evaluation of performance of circuit designs. These tools enable the designer to estimate performance, to identify components which are contributing to a performance reduction and to redesign those components during the design process.
Limiting power consumption in high performance microprocessors ensures cost effective desk top computers and faster portable computers. The rapidly growing portable computer market requires power efficient central processing units that permit higher performance while achieving an acceptable battery life. Personal computers could become more expensive as a result of increased cooling and power delivery costs necessary for improved processor performance, if power dissipation is not controlled. Ideally, processor performance could be improved without correspondingly increased power delivery and cooling costs.
In high performance microprocessors, no one design element is responsible for power consumption. Moreover, any attempt to analyze power consumption in such high performance systems is made more complex because the design methodology varies for different design blocks.
Many of the attributes of high performance designs, such as power dissipation, have complex interactions with other design attributes such as performance. As the design develops, it becomes progressively more difficult to change the design features to re-balance those attributes. As the design becomes more mature, changes can have a substantial impact on cost and schedule. Unfortunately, early in the design stage the circuit design may still be at a high level of abstraction. As the design matures the circuit may progress through refinements from a high level functional description to a structural description to a logic level and ultimately to a detailed gate level. Optimizing attributes early is advantageous for the reasons described above; however, it would appear to be difficult to assess power use accurately early in the design process when the circuit in question is only abstractly described.
As a result, there is a need for a tool that predicts the power dissipation of electronic systems early enough in the design process. Assessing the power saving features early in the design enables power saving features to be included in the design before the design is too mature to readily allow such modifications to be made without excessive costs.
Because of the complexity of electronic systems, such as microprocessors, any estimating tool must handle large, complex and often customized data path blocks, synthesized and nonsynthesized logic, mixed logic styles, such as domino and static styles, and clock and data buffer models. There is a need for such a power estimation tool which accounts for these variations in a way that makes it easy for the designer to determine the power usage of the system and to balance the power dissipation against other design criteria such as performance, size, testability and the like.
An early power estimation may be developed before the circuit design is well defined with sufficient accuracy to allow designers to optimize the power dissipation of a high performance system while other attributes such as area, floor plan or performance are still being evaluated.
In accordance with one aspect of the present invention, a method of estimating power use by a proposed electronic system design before the design is completed includes the step of developing a power model for various components of the design at the functional block level. The power use by the design is then estimated.
In accordance with another aspect of the present invention, a method of estimating power use by a proposed electronic system design before the design is completed includes the step of developing a hardware description language (xe2x80x9cHDLxe2x80x9d) description of the proposed design. The HDL description is then used to develop a measure of the power use by the proposed design.
In accordance with yet another aspect of the present invention, a method of estimating power dissipation includes the step of estimating the power use of an electronic system. The estimated power use is tuned to account for specific design elements of the system.
In accordance with another aspect of the present invention, a method of estimating power use of the proposed electronic system design before the design is finalized includes the step of estimating the power use of the overall system excluding data and clock buffers. The power use of the data and the clock buffers is empirically estimated and a measure of the number of data and clock buffers in the system is developed. This data and clock buffer measure is added to the estimated system power use of the overall system.